1. Field of the Invention
The present invention generally relates to a semiconductor apparatus, and more particularly to a semiconductor apparatus having a large-size bus connection (super connection) which attention is currently focused on.
2. Description of the Related Art
A large-size bus connection (supper connection) is a wiring technology that employs a large-size bus wiring layer having a comparatively large width in a range of 5 xcexcm to 10 xcexcm. The large-size bus connection is expected to make it possible to provide a high-speed operation of semiconductor apparatus with low power consumption.
The large-size bus connection has the following advantages over a normal-size bus connection that is formed in a conventional semiconductor apparatus through micromachining:
1) it provides a small electrical resistance because the width of the wiring layer is large,
2) it provides a small parasitic capacity because the inter-layer distance between the bulk and the insulating layer and the wiring intervals of the large-size bus connection are large, and
3) it is suited for a high-speed operation of semiconductor devices because the time constant of the large-size bus is very small.
The packaging areas of semiconductor devices have been reduced on a yearly basis, and high-density implementation methods, such as ball-grid array (BGA), have been developed. When the BGA method is used, the bumps are arrayed on the surface of a semiconductor chip. The re-wiring method is provided to connect the bumps with the integrated circuit of the semiconductor chip. The re-wiring method employs a wiring layer including a pattern of wiring on the resin layer, such as polyimide resin, which is provided on the chip surface. The wiring layer, used in the re-wiring method, has a relatively large width, and it may be considered the large-size bus connection.
Further, a multi-chip semiconductor apparatus in which a logic device and a memory device coexist is known. For example, in the multi-chip semiconductor apparatus, the memory chip is overlaid onto the logic chip, and the connection of the memory device and the logic device is established by using the large-size bus wiring layer in the rewiring method, such as the bumps or the like. The large-size bus connection is provided to connect together the I/O (input/output) devices of the two chips.
Each of the logic chip and the memory chip includes a plurality of blocks, and each block contains the internal circuits. The internal circuits of the blocks and the I/O device are interconnected by an internal bus of each of the logic chip and the memory chip. For the purpose of connection of various circuits, the internal bus of each chip in the multi-chip semiconductor apparatus has a relatively large length of the wiring. In a conventional multi-chip semiconductor apparatus, the internal buses of the chips are a normal-size bus that is formed by using a micromachining process, although the length of the wiring is increasing as the degree of integration grows. The parasitic capacity of the internal buses in the conventional multi-chip semiconductor apparatus is increased due to the use of the normal-size bus connection, which will lower the operating speed of the apparatus and increase the power consumption of the apparatus. Hence, it is difficult for the conventional multi-chip semiconductor apparatus to provide a high-speed operation with low power consumption if the degree of integration of the circuits in the chip grows.
An object of the present invention is to provide a semiconductor apparatus that operates at a high speed with low power consumption by using the large-size bus connection as the signal transmission line between the circuit components of the chip.
Another object of the present invention is to provide a semiconductor apparatus that has a large-size bus wiring structure configured to suit to both the wafer test conducted before formation of the large-size bus connection and the chip test or operating test conducted after the formation of the large-size bus connection.
Another object of the present invention is to provide a multi-chip semiconductor apparatus that operates at a high speed with low power consumption by using the large-size bus connection as the signal transmission line between the circuit components of the chip.
Another object of the present invention is to provide a semiconductor apparatus that provides flexibility of the layout of the circuit components by using the large-size bus connection.
The above-mentioned objects of the present invention are achieved by a semiconductor apparatus having circuit components, the semiconductor apparatus comprising: a first bus which interconnects the circuit components; a second bus which interconnects the circuit components; and a switching unit which outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another, the second bus having a size larger than a size of the first bus.
The above-mentioned objects of the present invention are achieved by a semiconductor apparatus having circuit components, the semiconductor apparatus comprising: a first bus which interconnects the circuit components; a second bus which interconnects the circuit components; and a switching unit which outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another, the switching unit being configured such that the first bus is selected only when a wafer test is conducted before formation of the second bus, and the second bus is selected at any time the semiconductor apparatus operates after the wafer test is conducted.
The above-mentioned objects of the present invention are achieved by a multi-chip semiconductor apparatus in which a first chip and a second chip coexist and each of the first and second chips includes circuit components, one of the first and second chips comprising: a first wiring layer which is provided on a semiconductor substrate; a second wiring layer which is provided on an insulating layer covering the first wiring layer, the second wiring layer including conductive lines each interconnecting the circuit components of said one of the first and second chips; a plurality of first electrodes which are provided in the first wiring layer; and a second electrode which is provided on each of the conductive lines, each conductive line being configured to interconnect the plurality of first electrodes and the second electrode.
The above-mentioned objects of the present invention are achieved by a semiconductor apparatus comprising: an external terminal; a first internal circuit connected to the external terminal via a first contact; a second internal circuit connected to the external terminal via a second contact; and a large-size bus connecting the external terminal to each of the first internal circuit and the second internal circuit, wherein the large-size bus is provided in a second wiring layer on an insulating layer covering a first wiring layer provided on a semiconductor chip, the second wiring layer contacting both the first and second contacts, and the external terminal being brought into contact with the second wiring layer, wherein the connection of the large-size bus enables the first internal circuit and the second internal circuit to be spaced apart each other.
In the semiconductor apparatus of one preferred embodiment of the invention, the large-size bus that has a size larger than a size of the normal-size bus is provided to interconnect the circuit components of the chip. The large-size bus connection to constitute the large-size bus has a small parasitic capacity and enables the operation at a low driving voltage, and it is possible to provide a high-speed operation of the semiconductor apparatus with low power consumption.
The multi-chip semiconductor apparatus of one preferred embodiment of the invention does not require the I/O devices that are needed to connect together the multiple chips as in the conventional multi-chip semiconductor apparatus. According to the multi-chip semiconductor apparatus of the present invention, the delay time is shortened and the power consumption is reduced.
Further, in the semiconductor apparatus of one preferred embodiment the invention, the large-size bus interconnects the circuit components via the external electrodes. The semiconductor apparatus of the present invention is effective in providing flexibility of the layout of the circuit components while providing high-speed operation with low power consumption.